This invention relates generally to microstructure and, more particularly, to microstructure adapted for use in a monolithic structure with a semiconductor integrated circuit.
As is known in the art, microstructures have been suggested for use in a wide range of applications, such as in accelerometers, bolometers, and transducers.
As is also known in the art, semiconductor integrated circuits, such as dynamic random access memories (DRAMs) include capacitors for storage of charge. As the size of the DRAM cell is reduced, it becomes difficult to form capacitors having a sufficient capacitance. This is because the capacitance is determined by, inter alia, the surface area of the plates forming the capacitor.
Generally, existing capacitors include a pair of conductive layers, typically doped polycrystalline silicon disposed therebetween a dielectric layer comprised of an oxide film, a nitride film, a combination thereof, or high dielectric material, such as Ta.sub.2 O.sub.5. As reported in U.S. Pat. No. 5,543,346, one technique used to increase the surface area of the plates of the capacitor is to form the polycrystalline layer as a multi-level structure and with spacers having a pin shape, a cylindrical shape, or a rectangular frame shape extending through the multi-layer structure. While the pin-shaped capacitor described therein may be useful in some application, it requires a relatively complex fabrication procedure. Further, many such fabrication techniques for silicon-based microstructure rely on doped polycrystalline silicon and the etching selectivity between materials having different doping concentrations. They thus require the use of such doping techniques as ion implantation. Further, the resulting structures are highly electrically conductive thereby limiting their applications.